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SX1231
WIRELESS & SENSING PRODUCTS
10. Revision History
Table 34 Revision History
DATASHEET
Revision
1
2
3
4
5
6
7
Date
Oct 2009
Nov 2009
April 2010
Nov 2010
Sept 2011
Sept 2012
March 2013
Comment
First FINAL datasheet version
Clarification and adjustment on the specification
Corrections throughout the document
Improve AGC setting description, Temp sensor description
Update DIOx mapping tables
Simplify and clarify the description of the AGC
Add temperature sensor ’s approximate measurement time
Optimize suggested frequency hopping sequences, section 4.2.5
Modify Listen mode resolution description
List in Section 9 the differences between chip versions V2a and V2b
Describe handling method for Packets larger than the FIFO size
Document AFC for low modulation index, timing diagrams, adjust Tana
Correct OCP default configuration
Document RegTestAfc at address 0x71
Add section describing setup for low modulation index systems
Add application schematics
Adjust Thermal Impedance value
Add description for the Continuous-time DAGC
Update Section 9 to reflect improvements of the chip V2c
Insert TSSOP package information
Improve PA dynamic Range description in section 3.4.6
Add RSSI linearity curve
Correction of DAGC setting when AfcLowBetaOn=1
Improve startup times description on section 4.2.3
State all Blocking and AM Rejection figures in dB
Provide table with Dcc cutoff frequencies
Add note on the behavior of PLL Lock indicator for wideband modulations
Add Bill Of Material information
Band extension down to 424 MHz
Clarification of RssiStart and RssiDone status when DAGC enabled, section 3.5.9
Clarification of packet handling procedure in RX mode for large packets, section 5.5.6
Add RegTestTcxo register description at address 0x59
BOM modification, section 7.3
Improve and update section 3.5.13 Bit Synchronizer description
PLL Bandwidth register description
Rev. 7 - June 2013
Page 87
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